In recent years, the size of integrated circuits (ICs) has dramatically increased in both size and number of transistors, resulting in higher power consumption. In typical IC designs, the clock distribution network, i.e., the clock tree, can consume from twenty to fifty percent of an IC's total active power. One important technique for reducing power consumption in IC designs is to reduce the power of an IC's clock distribution tree by gating portions of the IC that do not need to be clocked under certain conditions.
This process, known as “clock gating”, disables the clocks fed to logic blocks of the IC when the logic blocks are not currently enabled or otherwise in active use. Power consumption due to the clocking of logic blocks that are not directly involved with the current operation of the IC is thereby minimized.
Reference is now made to FIG. 1 that shows a partial logic circuit 100 that has not been clock gated. Circuit 100 includes a synchronous load-enable register 110 and a multiplexer (MUX) 120 implementing the load enabling. The clock input port provides the clock signal “CLK” which clocks register 110 every cycle. The enable port provides an enable signal “EN” that enables MUX 120, thereby allows data propagation from logic 130 to register 110. Obviously, there is no need to clock register 110 on every cycle, since the data at the input of register 110 does not change every clock cycle.
Reference is now made to FIG. 2 that shows a partial logic circuit 200 to which a clock gating technique is applied. In circuit 200, an AND gate 210 is used as the gating circuit. The clock and the enable ports are connected to AND gate 210 as its inputs. When the enable signal is set to a logic value ‘1’, data is input to register 110 synchronously with the clock signal “CLK”. On the other hand, when the enable signal is set to a logic value ‘0’, data is not input to register 110 irrespective of the clock signal. Accordingly, when there is no need for loading data to register 110, unnecessary power consumption can be avoided by outputting the enable signals of a logic zero synchronously with the clock signal. The AND gate 210 controls the load enable signal of register 110 thus MUX 120 is eliminated from the circuit.
The clock gating technique is well known in the art as an effective technique for reducing the dynamic power of a system. In fact, the amount of dynamic power reduction depends on the number of registers that are gated and the percentage of time that the gated clock (i.e., the output of AND gate 210) is enabled. However, gating all registers in the design increases the size of the IC. As a result, traditional approaches gate all the registers having size greater than a predefined threshold. Alternatively, registers to be clock gated are manually selected. These approaches are not optimal, in terms of power and area cost, as most of the savings can be achieved using only few clock gating structures.
It would be therefore advantageous to provide a more efficient approach for selecting registers that are candidates for clock gating implementation.